Phyical Design Engineer
- Full-time
Company Description
Founded in 1984, our client excels at developing complex chip designs where feature integration and innovation is a premium. Our client has more than 1,000 patents that are key to our more than 700 products serving more than 2,500 end customers globally, through both direct and distributor-based channel sales.
The company's headquarters are in Austin, Texas, with international locations in Europe, China and Japan
Job Description
The key to this job is STA or static timing analysis; we use a tool called Primetime
You will be responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout. Interface with other design groups to ensure time to market and quality of results. You will also participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation.
Qualifications
Ideal Candidate
This position requires a BSEE/MSEE and 5+ years industry experience in a Logic design or Physical Design position.
Candidate should preferably have strong knowledge of RTL design and must be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter, Primetime, Conformal LEC, and ATPG.
Ideal candidate will also have working knowledge of scan insertion, and ATPG.
Must have good communication, teamwork, and debug/analysis skills for designs, library and technology files.
Additional Information
Skills and Certifications
have the worked on/written timing constraints?
experience with clock tree synthesis?
scan insertion? dft?
rtl logic?