- San Jose, CA
6 month contract posiiton (with possible extensions)
Need a semiconductor engineer with over 5 years experience in the field of digital / ASIC design
Expertise in synthesis tools such as RTL Compiler or Design Compiler is must.
Experience with STA (Static Timing Analysis) tools such as Primetime and/or ETS is also necessary.
Must be familiar with backend layout tools such as Encounter for CTS (Clock Tree Synthesis),
Place & Route, and Timing closure.
Must be local to SF Bay area and available for face to face interview.
Must have: Synthesis" "Timing Analysis" "Layout" "Place & Route" "Encounter"
Good to have:: "RC" "RTL Compiler" "Clock Tree" "LEC" "Timing Closure" "Cadence tools" "ETS"
USA APPLICANTS ONLY
NO SPONSORSHIP PROVIDED