DFT Design Engineer - high speed SERDES IPs (AMD-25696)
- Sunnyvale, CA
Top engineering skills just isn't good enough for our Engineering teams, we need high creativity to solve some of the most vexing technical challenges that an engineer with face, anywhere. AMD is at the forefront of technology innovation of visual computing experience; our world evolves through the use of the products we create. AMD is the place where imagination becomes a reality.
AMD does not do this alone we work alongside of the strongest engineering teams building the products that are changing how we live, work, and play. AMD’s customer-centric design approach of integrating our industry changing IP with customer-specific IP creates tailor-made solutions of APUs, Discrete GPUs, and flexible System-on-a-Chip (SoC) design methodology.
Our teams deliver modular I/O controller design across all of AMD products: gaming consoles, hand held gaming devices, online gaming, home entertainment devices, high-performance computing, mobile computing and cloud computing products
DFT Engineer - I/O controller
Mixed Signal DFT team is seeking a candidate with experience and interest in design for test (DFT) and debug (DFD) solutions of high speed SERDES IPs, such as PCIe Gen1/Gen2/Gen3, GDDR5, DDR3/4, SATA, USB2.0/USB3.0 and analog IPs, such as ADC, DAC, PLL and DLLs.
Responsibilities would also include generating ATPG models from custom circuits and driving IO test features. Creates environment to generate test patterns and vectors to use on automated test equipment. Assists test engineers in bring up activities, silicon debug and validation of test vectors on tester.
What we look for:
- Strong fundamental knowledge of DFT techniques such as Scan/Memory BIST and Repair/JTAG/Boundary Scan/IEEE 1500.
- Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
- Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools.
- Strong knowledge in IO-loopback/IO-BIST.
- Knowledge in Verilog coding
- Exposure to scan compression and Memory BIST architecture is a plus.
- Exposure to logic syntheses, equivalency checking and timing analysis.
- Exposure to design for debug and silicon debug is a plus.
- Strong communication skills to work with geographically distributed groups
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