RTL Logic Designer ( lead a cluster)
- Santa Clara, CA
A modern processor typically has several cores, but most software only utilizes one core at a time. A VISC virtual core would allow for the use of all the cores, for better efficiency. “Technical Excellence Awards 2014” By Eric Griffith
Our Engineering Team has accomplished a breakthrough in CPU performance and power.
Benchmarks show that VISC handily outperformed an ARM Cortex-15 in every category - often by more than 2x or 3x.
Benchmarks show that two-core VISC can deliver the same performance as A15 while using just one-third the power. Conversely, a four-core VISC can crank out the roughly double the performance at the same power level
This is a very exciting time as we are turn our innovative technology into high volume computing products!
As a senior member (or technical lead) of the team developing a cutting edge micro-processor, you will be at the front end of this new product development cycle and your inputs will include micro-architecture specification and logic design for a high-performance, low-power CPU core.
- As RTL Engineer you will own development, assessment and refinement of RTL design to target power, performance, area and timing goals.
- Validation - Support testbench development and simulation for functional and performance verification. Performance exploration and correlation
- Explore high performance strategies and validate that the RTL design meets targeted performance.
- Work with design team members across disciplines (Logic, Circuits, PD, DFT) to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
This role calls for 10+ years of core CPU RTL design experience.
ability to lead a cluster.